HD64F2145 Datasheet, PDF (375/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

14.4.3 5(62 Signal Output Timing
When TCNT overflows in watchdog timer mode, the OVF bit in TCSR is set to 1. When the
RST/10, bit is 1 here, the internal reset signal is generated for the entire LSI. At the same time,
the low level signal is output from the 5(62 pin. The timing is shown in figure 14.5.
ø
TCNT
Overflow signal
(internal signal)
OVF
signal
H'FF
H'00
132 states
Internal reset
signal
518 states
Figure 14.5 Output Timing of 5(62 signal
14.5 Interrupt Sources
During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI).
The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be
cleared to 0 in the interrupt handling routine.
When the NMI interrupt request is selected in watchdog timer mode, an NMI interrupt request is
generated by an overflow.
Table 14.2 WDT Interrupt Source
Name
WOVI
Interrupt Source
TCNT overflow
Interrupt Flag
OVF
DTC Activation
Not possible
Rev. 2.0, 08/02, page 335 of 788