HD64F2145 Datasheet, PDF (591/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Slave CPU
Master CPU
ODR1 write
Write 1 to IRQ1E1
OBF1 = 0?
No
Yes
All bytes
No
transferred?
Yes
SERIRQ IRQ1 output
SERIRQ IRQ1
source clearance
Interrupt initiation
ODR1 read
Hardware operation
Software operation
Figure 19.8 HIRQ Flowchart (Example of Channel 1)
19.6 Usage Notes
19.6.1 Module Stop Mode Setting
LPC operation can be enabled or disabled using the module stop control register. The initial
setting is for LPC operation to be halted. Register access is enabled by canceling module stop
mode. For details, refer to section 26, Power-Down Modes.
19.6.2 Notes on Using Host Interface
The host interface provides buffering of asynchronous data from the host processor and slave
processor (this LSI), but an interface protocol that uses the flags in STR must be followed to avoid
data contention. For example, if the host and slave processor both try to access IDR or ODR at the
same time, the data will be corrupted. To prevent simultaneous accesses, IBF and OBF must be
used to allow access only to data for which writing has finished.
Unlike the IDR and ODR registers, the transfer direction is not fixed for the bidirectional data
registers (TWR). MWMF and SWMF are provided in STR to handle this situation. After writing
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