HD64F2145 Datasheet, PDF (333/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

12.9.3 Conflict between TCOR Write and Compare-Match
If a compare-match occurs during the T2 state of a TCOR write cycle as shown in figure 12.16,
the TCOR write takes priority and the compare-match signal is disabled. With TMR_X, a TICR
input capture conflicts with a compare-match in the same way as with a write to TCORC. In this
case also, the input capture takes priority and the compare-match signal is disabled.
TCOR write cycle by CPU
T1
T2
Ø
Address
TCOR address
Internal write signal
TCNT
N
N+1
TCOR
N
M
Compare-match signal
TCOR write data
Disabled
Figure 12.16 Conflict between TCOR Write and Compare-Match
Rev. 2.0, 08/02, page 293 of 788