HD64F2145 Datasheet, PDF (353/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Table 13.6 Examples of TCR and TCSR Settings
Register
Bit
Abbreviation
Contents Description
TCR in TMR_1 7
6
CMIEB
CMIEA
0
Interrupts due to compare-match and
0
overflow are disabled
5
OVIE
0
4 and 3 CCLR1 and CCLR0 11
TCNT is cleared by the rising edge of
the external reset signal (inverse of
the IVI signal)
2 to 0 CKS2 to CKS0
101
TCNT is incremented on the rising
edge of the external clock (IHI signal)
TCSR in TMR_1 3 to 0 OS3 to OS0
0011
Not changed by compare-match B;
output inverted by compare-match A
(toggle output): Division by 512
1001
When TCORB < TCORA, 1 output on
compare-match B, and 0 output on
compare-match A: Division by 256
TCR in FRT
6
IEDGB
0/1
0: FRC value is transferred to ICRB
on falling edge of input capture
input B (IHI divided signal
waveform)
1: FRC value is transferred to ICRB
on rising edge of input capture
input B (IHI divided signal
waveform)
1 and 0 CKS1 and CKS0 01
FRC is incremented on internal clock:
ø/8
TCSR in FRT 0
CCLRA
0
FRC clearing is disabled
Rev. 2.0, 08/02, page 313 of 788