HD64F2145 Datasheet, PDF (140/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

7. The CPU generates a vector address for the accepted interrupt and starts execution of the
interrupt handling routine at the address indicated by the contents of the vector address in the
vector table.
Program excution state
No
Interrupt generated?
Yes
Yes
NMI
No
No
An interrupt with interrupt
control level 1?
Yes
No
IRQ0
Yes
No
IRQ1
Yes
IBFI3
Yes
Hold pending
No
IRQ0
Yes
No
IRQ1
Yes
IBFI3
Yes
No
I=0
Yes
Save PC and CCR
I1
Read vector address
Branch to interrupt handling routine
Figure 5.4 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0
Rev. 2.0, 08/02, page 100 of 788