HD64F2145 Datasheet, PDF (660/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

26.1.2 Low-Power Control Register (LPWRCR)
LPWRCR controls power-down modes.
Bit Bit Name Initial Value R/W Description
7 DTON 0
R/W Direct Transfer On Flag
Specifies the operating mode to be entered after executing
the SLEEP instruction.
When the SLEEP instruction is executed in high-speed
mode or medium-speed mode:
0: Shifts to sleep mode, software standby mode, or watch
mode
1: Shifts directly to subactive mode, or shifts to sleep mode
or software standby mode
When the SLEEP instruction is executed in subactive
mode:
0: Shifts to subsleep mode or watch mode
1: Shifts directly to high-speed mode, or shifts to subsleep
mode
6 LSON 0
R/W Low-Speed On Flag
Specifies the operating mode to be entered after executing
the SLEEP instruction. This bit also controls whether to shift
to high-speed mode or subactive mode when watch mode
is cancelled.
When the SLEEP instruction is executed in high-speed
mode or medium-speed mode:
0: Shifts to sleep mode, software standby mode, or watch
mode
1: Shifts to watch mode or subactive mode
When the SLEEP instruction is executed in subactive
mode:
0: Shifts directly to watch mode or high-speed mode
1: Shifts to subsleep mode or watch mode
When watch mode is cancelled:
0: Shifts to high-speed mode
1: Shifts to subactive mode
Rev. 2.0, 08/02, page 620 of 788