HD64F2145 Datasheet, PDF (171/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

By program wait
By
pin
T₁
T₂
T_W
T_W
T_W
T₃
Ø
Address bus
/ (IOSE = 0)
Read
Data bus
Read data
Write
,
Data bus
Write data
Note: shown in Ø clock indicates the
pin sampling timing.
Figure 6.13 Example of Wait State Insertion Timing (Pin Wait Mode)
6.6 Burst ROM Interface
In this LSI, the external address space can be designated as the burst ROM space by setting the
BRSTRM bit in BCR to 1, and the burst ROM interface enabled. Consecutive burst accesses of a
maximum four or eight words can be performed only during CPU instruction fetch. 1 or 2 states
can be selected for burst ROM access.
6.6.1 Basic Operation Timing
The number of access states in the initial cycle (full access) of the burst ROM interface is
determined by the AST bit in WSCR. When the AST bit is set to 1, wait states can be inserted. 1
or 2 states can be selected for burst access according to the setting of the BRSTS1 bit in BCR.
Wait states cannot be inserted in a burst cycle. Burst accesses of a maximum four words is
performed when the BRSTS0 bit in BCR is cleared to 0, and burst accesses of a maximum eight
words is performed when the BRSTS0 bit in BCR is set to 1.
The basic access timing for the burst ROM space is shown in figures 6.14 and 6.15.
Rev. 2.0, 08/02, page 131 of 788