HD64F2145 Datasheet, PDF (368/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

14.3.2 Timer Control/Status Register (TCSR)
TCSR selects the clock source to be input to TCNT, and the timer mode.
• TCSR_0
Initial
Bit Bit Name Value
7
OVF
0
6
WT/,7 0
5
TME
0
4
—
0
3
RST/10, 0
R/W Description
R/(W)*¹ Overflow Flag
Indicates that TCNT has overflowed (changes from H’FF
to H’00).
[Setting condition]
When TCNT overflows (changes from H’FF to H’00)
However, when internal reset request generation is
selected in watchdog timer mode, OVF is cleared
automatically by the internal reset.
[Clearing conditions]
• When TCSR is read when OVF = 1*², then 0 is
written to OVF
• When 0 is written to TME
R/W Timer Mode Select
Selects whether the WDT is used as a watchdog timer or
interval timer.
0: Interval timer mode
1: Watchdog timer mode
R/W Timer Enable
When this bit is set to 1, TCNT starts counting.
When this bit is cleared, TCNT stops counting and is
initialized to H'00.
R/(W) Reserved
The initial value should not be modified.
R/W Reset or NMI
Selects to request an internal reset or an NMI interrupt
when TCNT has overflowed.
0: An NMI interrupt is requested
1: An internal reset is requested
Rev. 2.0, 08/02, page 328 of 788