HD64F2145 Datasheet, PDF (148/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

5.7.2 Block Diagram
Figure 5.9 shows a block diagram of the address break.
BAR
ABRKCR
Match
signal
Comparator
Control
logic
Address break
interrupt request
Internal address
Prefetch signal
(internal signal)
Figure 5.9 Address Break Block Diagram
5.7.3 Operation
If the CPU prefetches an address specified in BAR by setting ABRKCR and BAR, an address
break interrupt can be generated. This address break function generates an interrupt request to the
interrupt controller at prefetch, and determines the priority by the interrupt controller. When an
interrupt is accepted, an interrupt exception handling is activated after the current instruction has
been completed. Note that the interrupt mask control according to the I and UI bits in CCR of the
CPU is invalid to an address break interrupt.
To use the address break function, set each register as follows:
1. Set a break address in the A23 to A1 bits in BAR.
2. Set the BIE bit in ABRKCR to 1 to enable the address break.
When the BIE bit is cleared to 0, an address break is not requested.
When the setting conditions are satisfied, the CMF flag in ABRKCR is set to 1 to request an
interrupt. The interrupt source should be determined by the interrupt handling routine if necessary.
Rev. 2.0, 08/02, page 108 of 788