SH7144_08 Datasheet, PDF (95/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

3.4 Address Map
The address map for the operating modes are shown in figure 3.1.
3. MCU Operating Modes
Modes 0 and 1
On-chip ROM disabled mode
Mode 2
On-chip ROM enabled mode
Mode 3
Single-chip mode
H'00000000
H'003FFFFF
H'00400000
H'007FFFFF
H'00800000
H'00BFFFFF
H'00C00000
H'00FFFFFF
H'01000000
H'013FFFFF
H'01400000
CS0 space
CS1 space
CS2 space
CS3 space
CS4 space*
H'017FFFFF
H'01800000
CS5 space*
H'01BFFFFF
H'01C00000
CS6 space*
CS7 space*
H'01FFFFFF
H'02000000
H'FFFF7FFF
Reserved area
H'FFFF8000
On-chip peripheral
H'FFFFBFFF
I/O registers
H'FFFFC000
Reserved area
H'FFFFDFFF
H'FFFFE000
On-chip RAM (8 kbytes)
H'FFFFFFFF
H'00000000
H'0003FFFF
On-chip ROM (256 kbytes)
H'00040000
Reserved area
H'00200000
H'003FFFFF
CS0 space
H'00400000
H'007FFFFF
H'00800000
CS1 space
H'00BFFFFF
H'00C00000
CS2 space
H'00FFFFFF
H'01000000
H'011FFFFF
H'01200000
H'013FFFFF
H'01400000
CS3 space
Reserved area
CS4 space*
CS5 space*
H'017FFFFF
H'01800000
CS6 space*
H'01BFFFFF
H'01C00000
CS7 space*
H'01FFFFFF
H'02000000
H'FFFF7FFF
H'FFFF8000
Reserved area
On-chip peripheral
H'FFFFBFFF
I/O registers
H'FFFFC000
Reserved area
H'FFFFDFFF
H'FFFFE000
On-chip RAM (8 kbytes)
H'FFFFFFFF
H'00000000
H'0003FFFF
On-chip ROM (256 kbytes)
H'00040000
Reserved area
H'FFFF7FFF
H'FFFF8000
On-chip peripheral
H'FFFFBFFF
I/O registers
H'FFFFC000
H'FFFFDFFF
Reserved area
H'FFFFE000
On-chip RAM (8 kbytes)
H'FFFFFFFF
Note: * CS4 space to CS7 space are available only in the masked ROM version and ROM less version.
These spaces are reserved in the flash memory version and emulator.
Figure 3.1 Address Map for Each Operating Mode
Rev.4.00 Mar. 27, 2008 Page 51 of 882
REJ09B0108-0400