SH7144_08 Datasheet, PDF (146/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

7. User Break Controller (UBC)
Figure 7.1 shows a block diagram of the UBC.
Module bus
Bus
interface
UBCR
UBBR ^{UBAMRH UBARH}
UBAMRL UBARL
Break condition
comparator
User break
interrupt
generating
circuit
UBC
[Legend]
UBARH, UBARL: User break address registers H, L
UBAMRH, UBAMRL: User break address mask registers H, L
UBBR:
User break bus cycle register
UBCR:
User break control register
Interrupt request
Interrupt controller
Figure 7.1 User Break Controller Block Diagram
Rev.4.00 Mar. 27, 2008 Page 102 of 882
REJ09B0108-0400