SH7144_08 Datasheet, PDF (148/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

7. User Break Controller (UBC)
Bit
Bit Name
UBAMRH15 to UBM31 to
UBAMRH0
UBM16
UBAMRL15 to UBM15 to
UBAMRL0
UBM0
Initial Value R/W Description
All 0
R/W User Break Address Mask 31 to 16
0: Corresponding UBA bit is included in the
break conditions
1: Corresponding UBA bit is not included in the
break conditions
All 0
R/W User Break Address Mask 15 to 0
0: Corresponding UBA bit is included in the
break conditions
1: Corresponding UBA bit is not included in the
break conditions
7.2.3 User Break Bus Cycle Register (UBBR)
The user break bus cycle register (UBBR) is a 16-bit readable/writable register that sets the four
break conditions.
Bit
15 to 8
7
6
5
4
Bit Name
—
CP1
CP0
ID1
ID0
Initial Value R/W Description
All 0
R Reserved
These bits are always read as 0. The write
value should always be 0.
0
R/W CPU Cycle/DMAC, DTC Cycle Select 1 and 0
0
R/W These bits specify break conditions for CPU
cycles or DMAC/DTC cycles.
00: No user break interrupt occurs
01: Break on CPU cycles
10: Break on DTC or DMAC cycles
11: Break on both CPU and DMAC or DTC
cycles
0
R/W Instruction Fetch/Data Access Select1 and 0
0
R/W These bits select whether to break on
instruction fetch and/or data access cycles.
00: No user break interrupt occurs
01: Break on instruction fetch cycles
10: Break on data access cycles
11: Break on both instruction fetch and data
access cycles
Rev.4.00 Mar. 27, 2008 Page 104 of 882
REJ09B0108-0400