SH7144_08 Datasheet, PDF (740/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

22. User Debugging Interface (H-UDI)
22.3 Register Description
The H-UDI has the following registers. For the register addresses and register states in each
operating mode, refer to section 25, List of Registers.
• Instruction register (SDIR)
• Status register (SDSR)
• Data register H (SDDRH)
• Data register L (SDDRL)
• Bypass register (SDBPR)
Instructions and data can be input to the instruction register (SDIR) and data register (SDDR) by
serial transfer from the test data input pin (TDI). Data from the status register (SDSR), and SDDR
can be output via the test data output pin (TDO). The bypass register (SDBPR) is a one-bit register
that is connected to TDI and TDO in bypass mode. Except for SDBPR, all the registers can be
accessed by the CPU.
Table 22.2 shows the kinds of serial transfer that can be used with each of the H-UDI’s registers.
Table 22.2 Serial Transfer Characteristics of H-UDI Registers
Register
SDIR
SDSR
SDDRH
SDDRL
SDBPR
Serial Input
Possible
Not possible
Possible
Possible
Possible
Serial Output
Not possible
Possible
Possible
Possible
Possible
Rev.4.00 Mar. 27, 2008 Page 696 of 882
REJ09B0108-0400