SH7144_08 Datasheet, PDF (425/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

12. Watchdog Timer
12.3 Register Descriptions
The WDT has the following three registers. For details, see section 25, List of Registers. To
prevent accidental overwriting, TCSR, TCNT, and RSTCSR have to be written to in a method
different from normal registers. For details, see section 12.6.1, Notes on Register Access.
• Timer control/status register (TCSR)
• Timer counter (TCNT)
• Reset control/status register (RSTCSR)
12.3.1 Timer Counter (TCNT)
TCNT is an 8-bit readable/writable upcounter. When the timer enable bit (TME) in the timer
control/status register (TCSR) is set to 1, TCNT starts counting pulses of an internal clock selected
by clock select bits 2 to 0 (CKS2 to CKS0) in TCSR. When the value of TCNT overflows
(changes from H'FF to H'00), a watchdog timer overflow signal (WDTOVF) or interval timer
interrupt (ITI) is generated, depending on the mode selected in the WT/IT bit of TCSR.
The initial value of TCNT is H'00.
Rev.4.00 Mar. 27, 2008 Page 381 of 882
REJ09B0108-0400