SH7144_08 Datasheet, PDF (125/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

6. Interrupt Controller (INTC)
Bit
Bit Name Initial Value R/W Description
4
IRQ3S 0
R/W IRQ3 Sense Select
This bit sets the IRQ3 interrupt request detection
mode.
0: Interrupt request is detected on low level of IRQ3
input
1: Interrupt request is detected on edge of IRQ3 input
(edge direction is selected by ICR2)
3
IRQ4S 0
R/W IRQ4 Sense Select
This bit sets the IRQ4 interrupt request detection
mode.
0: Interrupt request is detected on low level of IRQ4
input
1: Interrupt request is detected on edge of IRQ4 input
(edge direction is selected by ICR2)
2
IRQ5S 0
R/W IRQ5 Sense Select
This bit sets the IRQ5 interrupt request detection
mode.
0: Interrupt request is detected on low level of IRQ5
input
1: Interrupt request is detected on edge of IRQ5 input
(edge direction is selected by ICR2)
1
IRQ6S 0
R/W IRQ6 Sense Select
This bit sets the IRQ6 interrupt request detection
mode.
0: Interrupt request is detected on low level of IRQ6
input
1: Interrupt request is detected on edge of IRQ6 input
(edge direction is selected by ICR2)
0
IRQ7S 0
R/W IRQ7 Sense Select
This bit sets the IRQ7 interrupt request detection
mode.
0: Interrupt request is detected on low level of IRQ7
input
1: Interrupt request is detected on edge of IRQ7 input
(edge direction is selected by ICR2)
Rev.4.00 Mar. 27, 2008 Page 81 of 882
REJ09B0108-0400