SH7144_08 Datasheet, PDF (210/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

9. Bus State Controller (BSC)
9.10 Access to On-chip Peripheral I/O Registers
On-chip peripheral I/O registers are accessed from the bus state controller as shown in table 9.3.
Refer to section 25, List of Registers, for more details.
Table 9.3 Access to On-chip Peripheral I/O Registers
On-chip
peripheral
module SCI
MTU,
PFC,
POE INTC PORT CMT A/D
UBC WDT DMAC DTC IIC
H-UDI
Connection 8 bits 16 bits 16 bits 16 bits 16 bits 8 bits 16 bits 16 bits 16 bits 16 bits 8 bits 16 bits
bus width
Number of 2 cyc
access
cycles
2 cyc
2 cyc
2 cyc
2 cyc
3 cyc
3 cyc
3 cyc
3 cyc
3 cyc
2 cyc
2 cyc
9.11 Cycles of No-Bus Mastership Release
The bus mastership is not released during one bus cycle. For example, when the longword read (or
write) access is performed to the 8-bit normal space, four memory accesses to the 8-bit normal
space are regarded as one bus cycle. In this bus cycle, the bus mastership is not released. In this
case, assuming that one memory access takes two states, the bus mastership is not released in eight
states.
8 bits
8 bits
8 bits
Cycle in which the bus
mastership is not released
8 bits
Figure 9.16 One Bus Cycle
9.12 CPU Operation when Program Is Located in External Memory
In this LSI, two words (two instructions) are fetched in one instruction fetch. This also applies to
the cases where program is located in external memory or the bus width of that external memory is
8 or 16 bits.
Also, if the program counter value is the odd word (2n+1) address or the program counter value
before branch is the even word (2n) address, 32 bits (two instructions) including each word
instruction are always fetched.
Rev.4.00 Mar. 27, 2008 Page 166 of 882
REJ09B0108-0400