SH7144_08 Datasheet, PDF (612/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

16. Compare Match Timer (CMT)
16.5.3 Contention between CMCNT Byte Write and Counter Incrementation
If an increment occurs during the T2 state of the CMCNT byte write cycle, the counter write has
priority, so no increment of the write data results on the side on which the write was performed.
The byte data on the side on which writing was not performed is also not incremented, so the
contents are those before the write.
Figure 16.8 shows the timing when an increment occurs during the T2 state of the CMCNT
(Upper byte) write cycle.
CMCNT write cycle
T1
T2
Pφ
Address
CMCNT (Upper byte)
Internal write
signal
CMCNT input
clock
CMCNT
(Upper byte)
N
CMCNT
(Lower byte)
X
M
CMCNT write data
X
Figure 16.8 CMCNT Byte Write and Increment Contention
Rev.4.00 Mar. 27, 2008 Page 568 of 882
REJ09B0108-0400