SH7144_08 Datasheet, PDF (227/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

10. Direct Memory Access Controller (DMAC)
On-Chip Peripheral Module Request Mode: In this mode a transfer is performed at the transfer
request signal (interrupt request signal) of an on-chip peripheral module. As indicated in table
10.3, there are ten transfer request signals: five from the multifunction timer pulse unit (MTU),
which are compare match or input capture interrupts; the receive data full interrupts (RXI) and
transmit data empty interrupts (TXI) of the two serial communication interfaces (SCI); and the
A/D conversion end interrupt (ADI1) of the A/D converter. When DMA transfers are enabled (DE
= 1, DME = 1, TE = 0, NMIF = 0, AE = 0), a transfer is performed upon the input of a transfer
request signal.
The transfer request source need not be the data transfer source or transfer destination. However,
when the transfer request is set by RXI (transfer request because SCI’s receive data is full), the
transfer source must be the SCI’s receive data register (RDR). When the transfer request is set by
TXI (transfer request because SCI’s transmit data is empty), the transfer destination must be the
SCI’s transmit data register (TDR). Also, if the transfer request is set to the A/D converter, the
data transfer destination must be the A/D converter register.
Table 10.3 Selecting On-Chip Peripheral Module Request Modes with RS Bits
DMAC Transfer DMA Transfer
Desti-
RS3 RS2 RS1 RS0 Request Source Request Signal Source nation Bus Mode
0 1 1 0 MTU
TGIA_0
Any* Any* Burst/cycle steal
0 1 1 1 MTU
TGIA_1
Any* Any* Burst/cycle steal
1 0 0 0 MTU
TGIA_2
Any* Any* Burst/cycle steal
1 0 0 1 MTU
TGIA_3
Any* Any* Burst/cycle steal
1 0 1 0 MTU
TGIA_4
Any* Any* Burst/cycle steal
1 0 1 1 A/D1
ADI1
ADDR1 Any* Burst/cycle steal
1 1 0 0 SCI0 transmit block TXI_0
Any* TDR0 Burst/cycle steal
1 1 0 1 SCI0 receiver block RXI_0
RDR0 Any* Burst/cycle steal
1 1 1 0 SCI1 transmit block TXI_1
Any* TDR1 Burst/cycle steal
1 1 1 1 SCI1 receiver block RXI_1
RDR1 Any* Burst/cycle steal
Notes: MTU: Multifunction timer pulse unit.
SCI0, SCI1: Serial communications interface channels 0 and 1.
ADDR1: A/D converter’s A/D register.
TDR_0, TDR_1: SCI_0 and SCI_1 transmit data registers.
RDR_0, RDR_1: SCI_0 and SCI_1 receive data registers.
* External memory, memory-mapped external device, on-chip memory, and on-chip
peripheral module (excluding DMAC, DTC, BSC, and UBC).
Rev.4.00 Mar. 27, 2008 Page 183 of 882
REJ09B0108-0400