SH7144_08 Datasheet, PDF (449/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

13. Serial Communication Interface (SCI)
• Smart card interface mode (when SMIF in SDCR is 1)
Bit Bit Name Initial Value R/W Description
7
TIE
0
R/W Transmit Interrupt Enable
When this bit is set to 1, a TXI interrupt request is
enabled.
TXI interrupt request cancellation can be performed
by reading 1 from the TDRE flag in SSR, then
clearing it to 0, or clearing the TIE bit to 0.
6
RIE
0
R/W Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt
requests are enabled.
RXI and ERI interrupt request cancellation can be
performed by reading 1 from the RDRF, FER, PER, or
ORER flag in SSR, then clearing the flag to 0, or
clearing the RIE bit to 0.
5
TE
0
R/W Transmit Enable
When this bit is set to 1, transmission is enabled.
In this state, serial transmission is started when
transmit data is written to TDR and the TDRE flag in
SSR is cleared to 0.
SMR setting must be made to decide the transfer
format before setting the TE bit to 1. When this bit is
cleared to 0, transmit operation is disabled, and the
TDRE flag in SSR is fixed to 1.
4
RE
0
R/W Receive Enable
When this bit is set to 1, reception is enabled.
Serial reception is started in this state when a start bit
is detected in asynchronous mode or synchronous
clock input is detected in clocked synchronous mode.
SMR setting must be made to decide the receive
format before setting the RE bit to 1.
Clearing the RE bit to 0 disables reception and does
not affect the RDRF, FER, PER, and ORER flags,
which retain their states.
Rev.4.00 Mar. 27, 2008 Page 405 of 882
REJ09B0108-0400