SH7144_08 Datasheet, PDF (512/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

14. I²C Bus Interface (IIC) Option
14.1 Features
• Selection of addressing or non-addressing format
I²C bus format: addressing format with an acknowledge bit, master and slave operation
Synchronous serial format: non-addressing format without an acknowledge bit, and with
master operation only
• This I²C bus format complies with the I²C bus interface advocated by Phillips.
• In the I²C bus format, two slave addresses are specifiable for a single device.
• Automatic creation of start and stop conditions in master mode of the I²C bus format
• Selectable acknowledge output level during reception in the I²C bus format
• Automatic loading of the acknowledge bit is available during transmission in the I²C bus
format.
• A wait function is available in the I²C bus format in the master mode.
After all data other than the acknowledge bit has been transferred, the system can be placed in
the wait state by setting SCL low. The wait state can be cancelled by clearing the interrupt flag
to 0.
• A wait function is available in the I²C bus format.
After all data other than the acknowledge bit has been transferred, a request to enter the wait
state can be issued by setting SCL low. The request to enter the wait state is cleared when the
next transfer becomes possible.
• Interrupt sources
Data transfer end (including when a transition to transmit mode is made in the I²C bus format,
when data in ICDR is transferred, or during a wait state)
Address match: when any slave address matches or the general call address is received in slave
receive mode of the I²C bus format (including address reception after loss in master
contention)
Loss of arbitration
Start condition detection (in master mode)
Stop condition detection (in slave mode)
• Sixteen variants of the internal clock are selectable in the master mode.
• Direct bus drive (SCL/SDA pin)
Pins SCL0 and SDA0 function as NMOS open-drain output.
Rev.4.00 Mar. 27, 2008 Page 468 of 882
REJ09B0108-0400