SH7144_08 Datasheet, PDF (533/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

14. I²C Bus Interface (IIC) Option
Bit Bit Name Initial Value R/W Description
0 ACKB 0
R/W Acknowledge
This bit stores the acknowledgements.
Transmit mode:
[Setting condition]
• Reception of 1 as an acknowledge bit when ACKE is 1
in transmit mode.
[Clearing conditions]
• Reception of 0 as an acknowledge bit when ACKE is 1
in transmit mode.
• Writing 0 to the ACKE bit
Receive mode:
0: After reception of data, 0 is output as acknowledge data
1: After reception of data, 1 is output as acknowledge data
When this bit is read, the value that was loaded here (the
value returned from the receiving device) is read during
transmission (TRS = 1). During receive operations (TRS =
0), the value that was set is read.
When this bit is written, acknowledge data that is returned
after receiving is rewritten regardless of the TRS value. If
the ICSR register flag is written using bit-manipulation
instructions, the acknowledge data should be set again
since the acknowledge data setting is rewritten by the
reading value of ACKB bit.
Write the ACKE bit to 0 to clear the ACKB flag to 0, before
transmission is ended and a stop condition is issued in
master mode, or before transmission is ended and SDA is
released to issue a stop condition by a master device.
Note: * Only 0 can be written to clear the flag.
Rev.4.00 Mar. 27, 2008 Page 489 of 882
REJ09B0108-0400