SH7144_08 Datasheet, PDF (192/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

9. Bus State Controller (BSC)
Bit Bit Name Initial Value R/W Description
11
IW11
1
10
IW10
1
R/W Idle cycles in CS1 and CS5 space cycles
R/W _{After read access to the CS1 and CS5 spaces, these bits}
insert idle cycles (1) when the write cycle to the CS1
space continues, (2) when the write cycle to the CS5
space continues, or (3) when continuous access is made
to CS spaces except for the CS1 and CS5 spaces.
00: No idle cycle inserted after access to the CS1 and
CS5 spaces
01: One idle cycle inserted after access to the CS1 and
CS5 spaces
10: Two idle cycles inserted after access to the CS1 and
CS5 spaces
11: Three idle cycles inserted after access to the CS1
and CS5 spaces
9
IW01
1
8
IW00
1
R/W Idle cycles in CS0 and CS4 space cycles
R/W _{After read access to the CS0 and CS4 spaces, these bits}
insert idle cycles (1) when the write cycle to the CS0
space continues, (2) when the write cycle to the CS4
space continues, or (3) when continuous access is made
to CS spaces except for the CS0 and CS4 spaces.
00: No idle cycle inserted after access to the CS0 and
CS4 spaces
01: One idle cycle inserted after access to the CS0 and
CS4 spaces
10: Two idle cycles inserted after access to the CS0 and
CS4 spaces
11: Three idle cycles inserted after access to the CS0
and CS4 spaces
Rev.4.00 Mar. 27, 2008 Page 148 of 882
REJ09B0108-0400