SH7144_08 Datasheet, PDF (185/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

9.4 Address Map
Figure 9.2 shows the address format used by this LSI.
9. Bus State Controller (BSC)
A31 to A24
A23, A22 A21
A0
Output address:
Output from the address pins
CS space selection:
Decoded, outputs CS0 to CS7 when A31 to A24 = 00000000 or 00000001
Space selection:
Not output externally; used to select the type of space
On-chip ROM space or CS space when 00000000 or 00000001 (H'00 or H'01)
Reserved (do not access) when 00000010 to 11111110 (H'02 to H'FE)
On-chip peripheral module space or on-chip RAM space when 11111111 (H'FF)
Figure 9.2 Address Format
This chip uses 32-bit addresses:
• Bits A31 to A24 are used to select the type of space and are not output externally.
• Bits A23 and A22 are decoded and output as chip select signals (CS0 to CS7) for the
corresponding areas when bits A31 to A24 are 00000000 or 00000001.
• Bits A21 to A0 are output externally.
Table 9.2 shows the address map.
Rev.4.00 Mar. 27, 2008 Page 141 of 882
REJ09B0108-0400