SH7144_08 Datasheet, PDF (604/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

16. Compare Match Timer (CMT)
16.2 Register Descriptions
The CMT has the following registers. For details on register addresses and register states during
each processing, refer to section 25, List of Registers.
• Compare match timer start register (CMSTR)
• Compare match timer control/status register_0 (CMCSR_0)
• Compare match timer counter_0 (CMCNT_0)
• Compare match timer constant register_0 (CMCOR_0)
• Compare match timer control/status register_1 (CMCSR_1)
• Compare match timer counter_1 (CMCNT_1)
• Compare match timer constant register_1 (CMCOR_1)
16.2.1 Compare Match Timer Start Register (CMSTR)
The compare match timer start register (CMSTR) is a 16-bit register that selects whether to
operate or halt the channel 0 and channel 1 counters (CMCNT).
Bit
Bit Name Initial Value R/W
15 to 2 ⎯
All 0
R
1
STR1 0
R/W
0
STR0 0
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Count Start 1
This bit selects whether to operate or halt compare
match timer counter_1. (CMCNT_1)
0: CMCNT_1 count operation halted
1: CMCNT_1 count operation
Count Start 0
This bit selects whether to operate or halt compare
match timer counter_0. (CMCNT_0)
0: CMCNT_0 count operation halted
1: CMCNT_0 count operation
Rev.4.00 Mar. 27, 2008 Page 560 of 882
REJ09B0108-0400