SH7144_08 Datasheet, PDF (429/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

12.4 Operation
12. Watchdog Timer
12.4.1 Watchdog Timer Mode
To use the WDT as a watchdog timer, set the WT/IT and TME bits of TCSR to 1. Software must
prevent TCNT overflow by rewriting the TCNT value (normally by writing H'00) before overflow
occurs. No TCNT overflows will occur while the system is operating normally, but if TCNT fails
to be rewritten and overflows occur due to a system crash or the like, a WDTOVF signal is output
externally. The WDTOVF signal can be used to reset the system. The WDTOVF signal is output
for 128φ clock cycles.
If the RSTE bit in RSTCSR is set to 1, a signal to reset the chip will be generated internally
simultaneous to the WDTOVF signal when TCNT overflows. Either a power-on reset or a manual
reset can be selected by the RSTS bit in RSTCSR. The internal reset signal is output for 512 φ
clock cycles.
When a WDT overflow reset is generated simultaneously with a reset input at the RES pin, the
RES reset takes priority, and the WOVF bit in RSTCSR is cleared to 0.
The following are not initialized by a WDT reset signal:
• Port output enable (POE) registers of MTU
• Pin function controller (PFC) registers
• I/O port registers
• Reset control/status register (RSTCSR) of watchdog timer (WDT)
These registers are initialized only by an external power-on reset.
Besides, TCNT and TCSR of the WDT are not initialized by a manual reset from the MRES pin,
but are initialized by an internal manual reset generated by a WDT overflow.
Rev.4.00 Mar. 27, 2008 Page 385 of 882
REJ09B0108-0400