SH7144_08 Datasheet, PDF (127/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

6. Interrupt Controller (INTC)
Bit Bit Name Initial Value R/W Description
9
IRQ3ES1 0
8
IRQ3ES0 0
R/W This bit sets the IRQ3 interrupt request edge
R/W ^{detection mode.}
00: Interrupt request is detected on falling edge of
IRQ3 input
01: Interrupt request is detected on rising edge of
IRQ3 input
10: Interrupt request is detected on both of falling
and rising edge of IRQ3 input
11: Cannot be set
7
IRQ4ES1 0
6
IRQ4ES0 0
R/W This bit sets the IRQ4 interrupt request edge
R/W ^{detection mode.}
00: Interrupt request is detected on falling edge of
IRQ4 input
01: Interrupt request is detected on rising edge of
IRQ4 input
10: Interrupt request is detected on both of falling
and rising edge of IRQ4 input
11: Cannot be set
5
IRQ5ES1 0
4
IRQ5ES0 0
R/W This bit sets the IRQ5 interrupt request edge
R/W ^{detection mode.}
00: Interrupt request is detected on falling edge of
IRQ5 input
01: Interrupt request is detected on rising edge of
IRQ5 input
10: Interrupt request is detected on both of falling
and rising edge of IRQ5 input
11: Cannot be set
3
IRQ6ES1 0
2
IRQ6ES0 0
R/W This bit sets the IRQ6 interrupt request edge
R/W ^{detection mode.}
00: Interrupt request is detected on falling edge of
IRQ6 input
01: Interrupt request is detected on rising edge of
IRQ6 input
10: Interrupt request is detected on both of falling
and rising edge of IRQ6 input
11: Cannot be set
Rev.4.00 Mar. 27, 2008 Page 83 of 882
REJ09B0108-0400