SH7144_08 Datasheet, PDF (15/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

11.5.2 DTC/DMAC Activation.......................................................................................312
11.5.3 A/D Converter Activation....................................................................................312
11.6 Operation Timing..............................................................................................................313
11.6.1 Input/Output Timing ............................................................................................313
11.6.2 Interrupt Signal Timing........................................................................................318
11.7 Usage Notes ......................................................................................................................321
11.7.1 Module Standby Mode Setting.............................................................................321
11.7.2 Input Clock Restrictions.......................................................................................321
11.7.3 Caution on Period Setting ....................................................................................322
11.7.4 Contention between TCNT Write and Clear Operations .....................................322
11.7.5 Contention between TCNT Write and Increment Operations..............................323
11.7.6 Contention between TGR Write and Compare Match .........................................324
11.7.7 Contention between Buffer Register Write and Compare Match ........................325
11.7.8 Contention between TGR Read and Input Capture..............................................326
11.7.9 Contention between TGR Write and Input Capture.............................................327
11.7.10 Contention between Buffer Register Write and Input Capture ............................328
11.7.11 TCNT2 Write and Overflow/Underflow Contention in Cascade Connection......328
11.7.12 Counter Value during Complementary PWM Mode Stop ...................................330
11.7.13 Buffer Operation Setting in Complementary PWM Mode...................................330
11.7.14 Reset Sync PWM Mode Buffer Operation and Compare Match Flag .................331
11.7.15 Overflow Flags in Reset Synchronous PWM Mode ............................................332
11.7.16 Contention between Overflow/Underflow and Counter Clearing........................333
11.7.17 Contention between TCNT Write and Overflow/Underflow...............................334
11.7.18 Cautions on Transition from Normal Operation or PWM Mode 1 to
Reset-Synchronous PWM Mode..........................................................................334
11.7.19 Output Level in Complementary PWM Mode and Reset-Synchronous
PWM Mode..........................................................................................................335
11.7.20 Interrupts in Module Standby Mode ....................................................................335
11.7.21 Simultaneous Capture of TCNT_1 and TCNT_2 in Cascade Connection...........335
11.7.22 Note on Buffer Operation Setting ........................................................................335
11.8 MTU Output Pin Initialization ..........................................................................................336
11.8.1 Operating Modes..................................................................................................336
11.8.2 Reset Start Operation ...........................................................................................336
11.8.3 Operation in Case of Re-Setting Due to Error During Operation, Etc. ................337
11.8.4 Overview of Initialization Procedures and Mode Transitions in Case of
Error during Operation, etc. .................................................................................338
11.9 Port Output Enable (POE).................................................................................................368
11.9.1 Features................................................................................................................368
11.9.2 Pin Configuration.................................................................................................370
11.9.3 Register Descriptions ...........................................................................................370
Rev.4.00 Mar. 27, 2008, Page xv of xliv
REJ09B0108-0400