SH7144_08 Datasheet, PDF (569/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

14. I²C Bus Interface (IIC) Option
Table 14.7 Examples of Operations in which the DTC Is Used
Item
Master Transmit Master Receive Slave Transmit Slave Receive
Mode
Mode
Mode
Mode
Slave address + DTC transmission
R/W bit
(ICDR write)
transmission/recep
tion
CPU transmission
(ICDR write)
CPU reception
(ICDR read)
CPU reception
(ICDR read)
Dummy data read ⎯
CPU processing ⎯
⎯
(ICDR read)
Main unit data DTC transmission DTC reception
transmission/recep (ICDR write)
(ICDR read)
tion
DTC transmission DTC reception
(ICDR write)
(ICDR read)
Final frame
processing
Unnecessary
CPU reception
(ICDR read)
Unnecessary
CPU reception
(ICDR read)
Setting the
Transmission:
Reception:
number of frames Number of actual Number of actual
of data to be
frames of data + 1 frames of data
transferred in DTC (+1 represents the
frame for slave
address + R/W
bits)
Transmission:
Number of actual
frames of data
Reception:
Number of actual
frames of data
Rev.4.00 Mar. 27, 2008 Page 525 of 882
REJ09B0108-0400