SH7144_08 Datasheet, PDF (181/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

9. Bus State Controller (BSC)
Section 9 Bus State Controller (BSC)
The bus state controller (BSC) divides up the address spaces and outputs control signals for
various types of memory. This enables memories like SRAM and ROM to be connected directly
to the chip without external circuitry.
9.1 Features
The BSC has the following features:
• Address space is divided into four spaces
⎯ A maximum linear 2 Mbytes for on-chip ROM enabled mode, and a maximum 4 Mbytes
for on-chip ROM disabled mode, for address spaces CS0 and CS4
⎯ A maximum linear 4 Mbytes for address space CS1 to CS3 and CS5 to CS7
⎯ Bus width (8, 16, or 32 bits) can be selected for each space
⎯ Wait states can be inserted by software for each space
⎯ Wait state insertion with WAIT pin in external memory space access
⎯ Outputs control signals for each space according to the type of memory connected
• On-chip ROM and RAM interfaces
⎯ On-chip ROM and RAM access of 32 bits in 1 state
BSC1001A_020020030800
Rev.4.00 Mar. 27, 2008 Page 137 of 882
REJ09B0108-0400