SH7144_08 Datasheet, PDF (560/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

14. I²C Bus Interface (IIC) Option
14. Confirm that the ICDRF flag is set to 1, and then read ICDR.
15. Clear the IRIC flag to 0.
Start condition issuance
SCL
(Master output)
1
2
3
4
5
6
7
8
9
1
2
3
4
SDA
(Master output)
SDA
(Slave output)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Slave address
R/W
bit 7 bit 6 bit 5 bit 4
[6]
Data 1
A
IRIC
ICDRF
ICDRS
ICDRR
Address + R/W
Data 1
[7]
Address + R/W
User processing
[8] IRIC clear
[10] ICDR read
Figure 14.21 An Example of the Timing of Operations in Slave Receive Mode 1
(MLS = ACKB = 0, HNDS = 0)
Rev.4.00 Mar. 27, 2008 Page 516 of 882
REJ09B0108-0400