SH7144_08 Datasheet, PDF (588/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

15. A/D Converter
15.3 Register Descriptions
The A/D converter has the following registers. For details on register addresses and register states
in each processing state, refer to section 25, List of Registers.
• A/D data register 0 (ADDR0)
• A/D data register 1 (ADDR1)
• A/D data register 2 (ADDR2)
• A/D data register 3 (ADDR3)
• A/D data register 4 (ADDR4)
• A/D data register 5 (ADDR5)
• A/D data register 6 (ADDR6)
• A/D data register 7 (ADDR7)
• A/D control/status register_0 (ADCSR_0)
• A/D control/status register_1 (ADCSR_1)
• A/D control register_0 (ADCR_0)
• A/D control register_1 (ADCR_1)
• A/D trigger select register (ADTSR)
15.3.1 A/D Data Registers 0 to 7 (ADDR0 to ADDR7)
ADDRs are 16-bit read-only registers. The conversion result for each analog input channel is
stored in ADDR with the corresponding number. (For example, the conversion result of AN4 is
stored in ADDR4.)
The converted 10-bit data is stored in bits 6 to 15. The lower 6 bits are always read as 0.
The data bus between the CPU and the A/D converter is 8 bits wide. The upper byte can be read
directly from the CPU, however the lower byte should be read via a temporary register. The
temporary register contents are transferred from the ADDR when the upper byte data is read.
When reading the ADDR, read the upper byte before the lower byte, or read in word unit.
The initial value of ADDR is H'0000.
Rev.4.00 Mar. 27, 2008 Page 544 of 882
REJ09B0108-0400