SH7144_08 Datasheet, PDF (523/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

14. I²C Bus Interface (IIC) Option
Bit Bit Name Initial Value R/W Description
3 ACKE
0
R/W Enables/Disables Acknowledge Bit
0: The value of the acknowledge bit is ignored to allow
the continuous transfer of data. The received value of
the acknowledge bits that are received do not affect
the ACKB bit; the value in the ACKB bit in ICSR
remains at 0.
1: When the value of the acknowledge bits received in
the I²C bus format is 1, transmission is suspended.
The acknowledge bit is used in two different ways,
depending on the situation. One case is that the
acknowledge bit is used as a kind of flag to indicate
whether or not processing for the reception of data has
been completed.
The other case is that acknowledge bit is fixed to 1.
2 BBSY
0
R/W Bus Busy
0 SCP
1
W Start/Stop Condition Issuance Disable
Master mode:
• Write 0 to BBSY and SCP: Issuing stop condition
• Write 1 to BBSY and 0 to SCP: Issuing start
condition and re-transmitting start condition
Slave mode:
• Writing to the BBSY flag is disabled
[BBSY setting condition]
• When SDA changes from high to low while SCL is
high, the system regards the start condition as
having been set.
[BBSY clearing condition]
• When SDA changes from low to high while SDA is
high, the system regards the stop condition as
having been set.
The start and stop conditions are issued by using the
MOV instruction.
The I²C bus interface must be set to master transmit
mode before the start condition is issued. Before writing
1 to BBSY and 0 to SCP, set MST and TRS to 1.
The BBSY flag may be read to confirm whether or not
the I²C bus (SCL, SDA) has been released.
The SCP bit is always read as 1. Data is not stored even
if 0 is written to the SCP bit.
Rev.4.00 Mar. 27, 2008 Page 479 of 882
REJ09B0108-0400