SH7144_08 Datasheet, PDF (837/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

26. Electrical Characteristics
26.3.14 AUD Timing
Table 26.16 shows AUD timing.
Table 26.16 AUD Timing
Conditions: V_CC = PLLV_CC =3.3 V ± 0.3 V, AV_CC = 3.3 V ± 0.3 V, AV_CC = V_CC ± 0.3 V,
AV_ref = 3.0 V to AV_CC , V_SS = PLLV_SS = AV_SS = 0 V, T_a = –20°C to +75°C
(regular specifications), T_a = –40°C to +85°C (wide-range specifications),
When programming or erasing flash memory, T_a = –20°C to +75°C.
Item
Symbol Min.
Max. Unit
AUDRST pulse width (Branch trace)
AUDRST pulse width (RAM monitor)
AUDMD setup time (Branch trace)
AUDMD setup time (RAM monitor)
Branch trace clock cycle
Branch trace clock duty
Branch trace data delay time
Branch trace data hold time
Branch trace SYNC delay time
Branch trace SYNC hold time
RAM monitor clock cycle
RAM monitor clock low pulse width
RAM monitor output data delay time
RAM monitor output data hold time
RAM monitor input data setup time
RAM monitor
input data hold
time
PE3/AUDATA3,
PE4/AUDATA2
Other AUDATA pins
t_AUDRSTW
t
AUDRSTW
t
AUDMDS
t
AUDMDS
t_BTCYC
t_BTCKW
t_BTDD
t_BTDH
t_BTSD
t
BTSH
t
RMCYC
t
RMCKW
t
RMDD
t_RMDHD
t_RMDS
t_RMDH
20
⎯
t_cyc
5
⎯
t
RMCYC
20
⎯
t
cyc
5
⎯
t
RMCYC
2
2
t_cyc
40
60
%
⎯
11
ns
−10
⎯
ns
⎯
10
ns
−10
⎯
ns
80
⎯
ns
35
⎯
ns
7
t −20 ns
RMCYC
5
⎯
ns
10
⎯
ns
15 + t_RMCYC − ⎯
ns
t_RMCKW
15
⎯
ns
RAM monitor SYNC setup time
t
10
RMSS
⎯
ns
RAM monitor
PA16/AUDSYNC
t
13 + t − ⎯
ns
RMSH
RMCYC
SYNC hold time
t
RMCKW
Other AUDSYNC pins
13
⎯
ns
Load conditions: AUDCK (output):
CL = 30 pF
AUDSYNC:
CL = 100 pF
AUDATA3 to AUDATA0: CL = 100 pF
Figure
Figure 26.27
Figure 26.28
Figure 26.29
Rev.4.00 Mar. 27, 2008 Page 793 of 882
REJ09B0108-0400