SH7144_08 Datasheet, PDF (212/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

10. Direct Memory Access Controller (DMAC)
Figure 10.1 is a block diagram of the DMAC.
On-chip ROM
On-chip RAM
On-chip
peripheral
module
DMAC module
Transfer
count
control
SARn
Register
control
DARn
Activation
control
DMATCRn
CHCRn
DREQ0, DREQ1
MTU
SCI0, SCI1
A/D 1
DEIn
DACK0, DACK1
DRAK0, DRAK1
External
ROM
External
RAM
External I/O
(memory
mapped)
External I/O
(with
acknowledge)
Request
priority
control
DMAOR
Bus interface
Bus state
controller
SARn: DMAC source address register
DARn: DMAC destination address register
DMATCRn: DMAC transfer count register
CHCRn: DMAC channel control register
DMAOR: DMAC operation register
n: 0, 1, 2, 3
Figure 10.1 DMAC Block Diagram
Rev.4.00 Mar. 27, 2008 Page 168 of 882
REJ09B0108-0400