SH7144_08 Datasheet, PDF (775/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

24. Power-Down Modes
24.4 Usage Notes
24.4.1 I/O Port Status
When a transition is made to software standby mode while the port high-impedance bit (HIZ) in
SBYCR is 0, I/O port states are retained. Therefore, there is no reduction in current consumption
for the output current when a high-level signal is output.
24.4.2 Current Consumption during Oscillation Stabilization Wait Period
Current consumption increases during the oscillation stabilization wait period.
24.4.3 On-Chip Peripheral Module Interrupt
Relevant interrupt operations cannot be performed in module standby mode. Consequently, if the
CPU enters module standby mode while an interrupt has been requested, it will not be possible to
clear the CPU interrupt source or the DMAC/DTC activation source.
Interrupts should therefore be disabled before entering module standby mode.
24.4.4 Writing to MSTCR1 and MSTCR2
MSTCR1 and MSTCR2 should only be written to by the CPU.
24.4.5 DMAC, DTC, or AUD Operation in Sleep Mode
In sleep mode, data should not be accessed by the DMAC, DTC, or AUD.
Rev.4.00 Mar. 27, 2008 Page 731 of 882
REJ09B0108-0400