SH7144_08 Datasheet, PDF (149/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

7. User Break Controller (UBC)
Bit
Bit Name Initial Value R/W Description
3
RW1
0
R/W Read/Write Select 1 and 0
2
RW0
0
R/W These bits select whether to break on read and/or
write cycles
00: No user break interrupt occurs
01: Break on read cycles
10: Break on write cycles
11: Break on both read and write cycles
1
SZ1
0
R/W Operand Size Select 1 and 0*
0
SZ0
0
R/W These bits select operand size as a break condition.
00: Operand size is not a break condition
01: Break on byte access
10: Break on word access
11: Break on longword access
Note: * When breaking on an instruction fetch, clear the SZ0 bit to 0. All instructions are
considered to be accessed in word-size (even when there are instructions in on-chip
memory and two instruction fetches are performed simultaneously in one bus cycle).
Operand size is word for instructions or determined by the operand size specified for
the CPU/DTC, DMAC data access. It is not determined by the bus width of the space
being accessed.
7.2.4 User Break Control Register (UBCR)
The user break control register (UBCR) is a 16-bit readable/writable register that enables or
disables user break interrupts.
Bit
Bit Name Initial Value R/W
15 to 1 —
All 0
R
0
UBID
0
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
User Break Disable
Enables or disables user break interrupt request
generation in the event of a user break condition
match.
0: User break interrupt request is enabled
1: User break interrupt request is disabled
Rev.4.00 Mar. 27, 2008 Page 105 of 882
REJ09B0108-0400