SH7144_08 Datasheet, PDF (581/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

14. I²C Bus Interface (IIC) Option
12. Points for caution when reading ICDR and accessing ICCR in slave transmit mode
In I²C bus interface slave transmit mode, do not read ICDR or do not read/write to ICCR
during the period shaded in figure 14.34. However, in interrupt handling processing that is
generated in synchronization with the rising edge of the 9th cycle of the clock, reading ICDR
or reading/writing to ICCR causes no error because the shaded period has passed before
making the transition to interrupt handling.
To handle interrupts securely, be sure to keep either of the following conditions.
⎯ Before starting the receive operation of the next slave address, finish the read of ICDR data
that has been received so far or the read/write of ICCR.
⎯ Monitor the BC2 to BC0 counter in ICMR; when the count is 000 (8th or 9th cycle of the
clock), wait for at least two transfer clocks to let the shaded period pass. Then, read ICDR
or read/write to ICCR.
SDA
R/W
SCL
8
TRS bit
Address reception
Erroneous waveforms
A
9
Write to ICDR
Bit 7
Data transmission
Period in which read from ICDR and read from
or write to ICCR are prohibited
(6 peripheral clocks)
Detection of rise of 9th transmit/receive clock
Figure 14.34 Timing for Reading ICDR and Accessing ICCR in Slave Transmit Mode
Rev.4.00 Mar. 27, 2008 Page 537 of 882
REJ09B0108-0400