SH7144_08 Datasheet, PDF (522/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

14. I²C Bus Interface (IIC) Option
Bit Bit Name Initial Value R/W Description
5 MST
0
R/W Master/Slave Select
4 TRS
0
R/W Transmission/Reception Select
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
Both MST and TRS bits will be cleared by hardware when
they lose in a bus contention in master mode of the I²C bus
format. The mode changes to slave receive mode. When
the I²C bus format is used in the slave-receive mode,
transmission or reception is automatically selected by the
hardware, according to the setting of the R/ W bit of the first
frame after the start condition has been satisfied.
Even if an attempt is made to change the TRS bit during the
transfer of data, the change is suspended until transmission
of data has been completed; the bit is then changed.
[MST clearing conditions]
1. Writing of 0 to this bit by software
2. Lose in a bus contention in master mode of the I²C bus
format
[MST setting conditions]
1. Writing of 1 to this bit by software (MST clearing
condition 1)
2. Writing of 1 to this bit after reading MST = 0 (MST
clearing condition 2)
[TRS clearing conditions]
1. Writing of 0 to this bit by software (except TRS setting
condition 3)
2. Writing of 0 to this bit after TRS = 1 is read (TRS setting
condition 3)
3. Lose in a bus contention in master mode of the I²C bus
format
[TRS setting conditions]
1. Writing of 1 to this bit by software (except TRS clearing
condition 3)
2. Writing of 1 to this bit after reading TRS = 0 (TRS
clearing condition 3)
3. When 1 is received as the R/W bit of the first frame
address matched in the I²C bus format in slave mode.
Rev.4.00 Mar. 27, 2008 Page 478 of 882
REJ09B0108-0400