SH7144_08 Datasheet, PDF (117/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

5. Exception Processing
5.6 Cases when Exception Sources Are not Accepted
When an address error or interrupt is generated directly after a delayed branch instruction or
interrupt-disabled instruction, it is sometimes not accepted immediately but stored instead, as
shown in table 5.10. In this case, it will be accepted when an instruction that can accept the
exception is decoded.
Table 5.10 Generation of Exception Sources Immediately after Delayed Branch Instruction
or Interrupt-Disabled Instruction
Exception Source
Point of Occurrence
Address Error Interrupt
Immediately after a delayed branch instruction*¹
Immediately after an interrupt-disabled instruction*²
Not accepted
Accepted
Not accepted
Not accepted
Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, and
BRAF
2. Interrupt-disabled instructions: LDC, LDC.L, STC, STC.L, LDS, LDS.L, STS, and STS.L
5.6.1 Immediately after Delayed Branch Instruction
When an instruction placed immediately after a delayed branch instruction (delay slot) is decoded,
neither address errors nor interrupts are accepted. The delayed branch instruction and the
instruction placed immediately after it (delay slot) are always executed consecutively, so no
exception processing occurs during this period.
5.6.2 Immediately after Interrupt-Disabled Instruction
When an instruction placed immediately after an interrupt-disabled instruction is decoded,
interrupts are not accepted. Address errors can be accepted.
Rev.4.00 Mar. 27, 2008 Page 73 of 882
REJ09B0108-0400