SH7144_08 Datasheet, PDF (290/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

11. Multi-Function Timer Pulse Unit (MTU)
11.3.5 Timer Status Register (TSR)
The TSR registers are 8-bit readable/writable registers that indicate the status of each channel. The
MTU has five TSR registers, one for each channel.
Bit Bit Name Initial Value R/W Description
7 TCFD 1
R
Count Direction Flag
Status flag that shows the direction in which TCNT counts
in channels 1, 2, 3, and 4.
In channel 0, bit 7 is reserved. It is always read as 1 and
the write value should always be 1.
6—
1
0: TCNT counts down
1: TCNT counts up
R
Reserved
This bit is always read as 1. The write value should always
be 1.
5 TCFU 0
R/(W)* Underflow Flag
Status flag that indicates that TCNT underflow has
occurred when channels 1 and 2 are set to phase counting
mode. Only 0 can be written, for flag clearing.
In channels 0, 3, and 4, bit 5 is reserved. It is always read
as 0 and the write value should always be 0.
4 TCFV 0
[Setting condition]
• When the TCNT value underflows (changes from
H'0000 to H'FFFF)
[Clearing condition]
• When 0 is written to TCFU after reading TCFU = 1
R/(W)* Overflow Flag
Status flag that indicates that TCNT overflow has
occurred. Only 0 can be written, for flag clearing.
[Setting condition]
• When the TCNT value overflows (changes from
H'FFFF to H'0000)
In channel 4, when the TCNT_4 value underflows
(changes from H'0001 to H'0000) in complementary
PWM mode, this flag is also set.
[Clearing condition]
• When 0 is written to TCFV after reading TCFV = 1
In cannel 4, when DTC is activated by TCIV interrupt
and the DISEL bit of DTMR in DTC is 0, this flag is
also cleared.
Rev.4.00 Mar. 27, 2008 Page 246 of 882
REJ09B0108-0400