SH7144_08 Datasheet, PDF (501/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

13. Serial Communication Interface (SCI)
TDRE
TEND
nth transfer frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
Retransferred frame
(DE)
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Transfer
frame n+1
Ds D0 D1 D2 D3 D4
Transfer to TSR from TDR
Transfer to TSR from TDR
Transfer to TSR
from TDR
FER/ERS
Figure 13.26 Retransfer Operation in SCI Transmit Mode
The timing for setting the TEND flag depends on the value of the GM bit in SMR. The TEND flag
generation timing is shown in figure 13.27.
I/O data
TXI
(TEND interrupt)
When GM = 0
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
12.5etu
Guard
time
When GM = 1
11.0etu
[Legend]
Ds:
Start bit
D0 to D7: Data bits
Dp:
Parity bit
DE:
Error signal
Figure 13.27 TEND Flag Generation Timing in Transmit Operation
Rev.4.00 Mar. 27, 2008 Page 457 of 882
REJ09B0108-0400