SH7144_08 Datasheet, PDF (165/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

8. Data Transfer Controller (DTC)
Bit Bit Name Initial Value R/W Description
7
DTVEC7 0
R/W DTC Software Activation Vectors 7 to 0
6
DTVEC6 0
5
DTVEC5 0
4
DTVEC4 0
3
DTVEC3 0
2
DTVEC2 0
1
DTVEC1 0
R/W These bits specify the lower eight bits of the vector
R/W
addresses for DTC activation by software.
R/W
A vector address is calculated as H'0400 + DTVEC
(7:0). Always specify 0 for DTVEC0. For example,
R/W
when DTVEC7 to DTVEC0 = H'10, the vector
R/W ^{address is H'0410. When the bit SWDTE is 0, these}
R/W
bits can be written to.
0
DTVEC0 0
R/W
Notes: 1. For the NMIF and AE bits, only a 0 write after a 1 read is possible.
2. For the SWDTE bit, a 1 write is always possible, but a 0 write is possible only after a 1
is read.
8.2.9 DTC Information Base Register (DTBR)
The DTBR is a 16-bit readable/writable register that specifies the upper 16 bits of the memory
address containing DTC transfer information. Always access the DTBR in word or longword
units. If it is accessed in byte units the register contents will become undefined at the time of a
write, and undefined values will be read out upon reads.
The initial value of DTBR is undefined.
Rev.4.00 Mar. 27, 2008 Page 121 of 882
REJ09B0108-0400