SH7144_08 Datasheet, PDF (558/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

14. I²C Bus Interface (IIC) Option
Continuous Receive Operation:
Figure 14.20 is a flowchart that gives an example of operations in slave receive mode (HNDS =
0).
Start
Initial setting
Set MST = 0 and TRS = 0
(ICCR)
Set ACKB = 0 (ICSR)
Set HNDS = 0 (SCRX)
Clear the IRIC flag in ICCR
No
ICDRF = 1?
Yes
Read ICDR
Read the IRIC flag in ICCR
No
IRIC = 1?
Yes
Clear the IRIC flag in ICCR
Read AASX, AAS, and ADZ flags in ICSR
AAS = 1
Yes
and ADZ =1?
No
Read the TRS bit in ICCR
Yes
TRS = 1?
No
Receive (n -2)th
No
byte?
Yes
Wait for one frame
Set ACKB = 1 (ICSR)
No
ICDRF = 1?
Yes
Read ICDR
Read the IRIC flag in ICCR
No
IRIC = 1?
Yes
ESTP = 1
Yes
or STOP = 1?
No
Clear the IRIC flag in ICCR
[1] Initial setting. Set slave receive mode.
[2] Read remained receive data.
[3] to [7] Wait for one byte to be received (slave address + R/W)
(IRIC is set at the 9th cycle of the clock).
[8] Clear the IRIC flag.
General call address processing
* Description omitted
Slave transmit mode
* n: Address + all receive byte
[9] Wait for ACKB setting and set acknowledge data for the final reception
(after the rise of the 9th cycle of (n-1)th byte data).
[10] Read receive data. The first read is a dummy read.
[11] Wait for one byte to be received
(IRIC is set at the 9 th cycle of the clock)
[12] Stop condition is detected
[13] Clear the IRIC flag.
No
ICDRF = 1?
Yes
Read ICDR
Clear the IRIC flag in ICCR
End
[14] Read final receive data.
[15] Clear the IRIC flag.
Figure 14.20 Example: Flowchart of Operations in Slave Transmit Mode (HNDS = 0)
Rev.4.00 Mar. 27, 2008 Page 514 of 882
REJ09B0108-0400