SH7144_08 Datasheet, PDF (743/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

22. User Debugging Interface (H-UDI)
22.3.3 Data Register (SDDR)
The data register (SDDR) comprises data register H (SDDRH) and data register L (SDDRL).
SDDRH and SDDRL are 16-bit registers that can be read and written to by the CPU. SDDR is
connected to TDO and TDI for serial data transfer to and from an external device.
32-bit data is input and output in serial data transfer. If data exceeding 32 bits is input, only the
last 32 bits will be stored in SDDR. Serial data is input starting with the MSB of SDDR (bit 15 of
SDDRH), and output starting with the LSB (bit 0 of SDDRL).
SDDR is not initialized by a reset, in software standby mode, or by the TRST signal.
The initial value of SDDR is undefined.
22.3.4 Bypass Register (SDBPR)
The bypass register (SDBPR) is a one-bit shift register. In bypass mode, SDBPR is connected to
TDI and TDO, and this LSI is bypassed in a board test. SDBPR cannot be read or written to by the
CPU.
Rev.4.00 Mar. 27, 2008 Page 699 of 882
REJ09B0108-0400