SH7144_08 Datasheet, PDF (561/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

14. I²C Bus Interface (IIC) Option
SCL
(Master output) ^{8 9 1 2 3 4 5 6 7 8 9}
SDA
(Master output)
bit 0
Data (n-2)
SDA
(Slave output)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
[11]
Data (n-1)
[11]
A
A
IRIC
Stop condition detection
123456789
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Data (n)
[11]
[12]
A
ICDRF
ICDRS Data (n-2)
Data (n-1)
Data (n)
ICDRR
User processing
Data (n-2)
[9] Wait time for one frame
Data (n-1)
[13] IRIC clear
[13] IRIC clear [10] ICDR read (Data (n -1))
[10] ICDR read
(Data (n -2))
[9] Set 1 to ACKB
Data (n)
[13] IRIC clear
[14] ICDR read
(Data (n))
[15] IRIC clear
Figure 14.22 An Example of the Timing of Operations in Slave Receive Mode 2
(MLS = ACKB = 0, HNDS = 0)
Rev.4.00 Mar. 27, 2008 Page 517 of 882
REJ09B0108-0400