SH7144_08 Datasheet, PDF (134/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

6. Interrupt Controller (INTC)
6.5 Interrupt Exception Processing Vectors Table
Table 6.2 lists interrupt sources and their vector numbers, vector table address offsets and interrupt
priorities.
Each interrupt source is allocated a different vector number and vector table address offset. Vector
table addresses are calculated from the vector numbers and address offsets. In interrupt exception
processing, the exception service routine start address is fetched from the vector table indicated by
the vector table address. For the details of calculation of vector table address, see table 5.4.
IRQ interrupts and on-chip peripheral module interrupt priorities can be set freely between 0 and
15 for each pin or module by setting interrupt priority registers A to J (IPRA to IPRJ). However,
the smaller vector number has interrupt source, the higher priority ranking is assigned among two
or more interrupt sources specified by the same IPR, and the priority ranking cannot be changed.
A power-on reset assigns priority level 0 to IRQ interrupts and on-chip peripheral module
interrupts. If the same priority level is assigned to two or more interrupt sources and interrupts
from those sources occur simultaneously, they are processed by the default priority order indicated
in table 6.2.
Table 6.2 Interrupt Exception Processing Vectors and Priorities
Interrupt
Source
External pin
User break
H-UDI
—
Interrupts
Name
Vector
No.
NMI
11
12
14
Reserved by system 15
IRQ0
64
IRQ1
65
IRQ2
66
IRQ3
67
IRQ4
68
IRQ5
69
IRQ6
70
IRQ7
71
Vector Table
Starting Address IPR
H'0000002C
—
H'00000030
—
H'00000038
—
H'0000003C
—
H'00000100
IPRA15 to IPRA12
H'00000104
IPRA11 to IPRA8
H'00000108
IPRA7 to IPRA4
H'0000010C
IPRA3 to IPRA0
H'00000110
IPRB15 to IPRB12
H'00000114
IPRB11 to IPRB8
H'00000118
IPRB7 to IPRB4
H'0000011C
IPRB3 to IPRB0
Default
Priority
High
Low
Rev.4.00 Mar. 27, 2008 Page 90 of 882
REJ09B0108-0400