SH7144_08 Datasheet, PDF (246/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

10. Direct Memory Access Controller (DMAC)
CK
DREQ
DRAK
Bus
cycle
DACK
CPU
CPU
CPU
Dummy
DMAC
DMAC
DMAC
Figure 10.21 Burst Mode, Single Address and Level Detection (Normal Operation)
CK
DREQ
DRAK
Bus
cycle
DACK
CPU
CPU
CPU DMAC(R) DMAC(W) DMAC(R) DMAC(W) DMAC(R) DMAC(W) DMAC(R) DMAC(W)
Figure 10.22 Burst Mode, Dual Address and Edge Detection
CK
DREQ
DRAK
Bus
cycle
DACK
CPU
CPU
CPU Dummy
DMAC
DMAC
DMAC
Figure 10.23 Burst Mode, Single Address and Edge Detection
DMAC
Rev.4.00 Mar. 27, 2008 Page 202 of 882
REJ09B0108-0400