SH7144_08 Datasheet, PDF (233/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

10. Direct Memory Access Controller (DMAC)
Two types of transfers are possible in the single address mode: (a) transfers between external
devices with DACK and memory-mapped external devices, and (b) transfers between external
devices with DACK and external memory. The only transfer requests for either of these is the
external request (DREQ). Figure 10.5 shows the DMA transfer timing for the single address
mode.
CK
A21–A0
CSn
D15–D0
WRH
WRL
DACK
Address output to external memory space
Data that is output from the external
device with DACK
WR signal to external memory space
DACK signal to external devices with
DACK (active low)
a. External device with DACK to external memory space
CK
A21–A0
CSn
D15–D0
RD
Address output to external memory space
Data that is output from external memory space
RD signal to external memory space
DACK
DACK signal to external device with DACK
(active low)
b. External memory space to external device with DACK
Figure 10.5 Example of DMA Transfer Timing in Single Address Mode
Rev.4.00 Mar. 27, 2008 Page 189 of 882
REJ09B0108-0400