SH7144_08 Datasheet, PDF (517/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

14. I²C Bus Interface (IIC) Option
14.3.3 Second Slave-Address Register (SARX)
SARX sets the transfer format and stores the second slave address. In slave mode of the I²C bus
format, if the FS bit is set to 0 and the upper seven bits of SARX match the upper seven bits of the
first frame received after a start condition, this module operates as the slave device specified by
the master device. SARX can be accessed only when the ICE bit in ICCR is set to 0.
Bit Bit Name
7 SVAX6
6 SVAX5
5 SVAX4
4 SVAX3
3 SVAX2
2 SVAX1
1 SVAX0
0 FSX
Initial Value
0
0
0
0
0
0
0
1
R/W Description
R/W Second Slave Address 6 to 0
R/W Set second slave address.
R/W
R/W
R/W
R/W
R/W
R/W Format Select X
In conjunction with the FS bit in SAR, this bit selects
the transfer format. See table 14.2.
Table 14.2 Transfer Format
SAR
FS
0
1
SARX
FSX
0
1
0
1
Operating Mode
I²C bus format
• Enables the slave addresses in SAR and SARX
• Enables the general call address
I²C bus format
• Enables the slave address in SAR
• Disables the slave address in SARX
• Enables the general call address
I²C bus format
• Disables the slave address in SAR
• Enables the slave address in SARX
• Disables the general call address
Synchronous serial format
• Disables the slave addresses in SAR and SARX
• Disables the general call address
Rev.4.00 Mar. 27, 2008 Page 473 of 882
REJ09B0108-0400