SH7144_08 Datasheet, PDF (428/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

12. Watchdog Timer
12.3.3 Reset Control/Status Register (RSTCSR)
RSTCSR is an 8-bit readable/writable register that controls the generation of the internal reset
signal when TCNT overflows, and selects the type of internal reset signal.
Bit Bit Name Initial Value R/W Description
7 WOVF
0
R/(W)* Watchdog Timer Overflow Flag
This bit is set when TCNT overflows in watchdog
timer mode. This bit cannot be set in interval timer
mode.
[Setting condition]
• Set when TCNT overflows in watchdog timer
mode
[Clearing condition]
• Cleared by reading WOVF, and then writing 0 to
WOVF
6 RSTE
0
R/W Reset Enable
Specifies whether or not an internal reset signal is
generated in the chip if TCNT overflows in watchdog
timer mode.
0: Internal reset signal is not generated even if
TCNT overflows
(Though this LSI is not reset, TCNT and TCSR in
WDT are reset)
1: Internal reset signal is generated if TCNT
overflows
5 RSTS
0
R/W Reset Select
Selects the type of internal reset generated if TCNT
overflows in watchdog timer mode.
0: Power-on reset
1: Manual reset
4 to 0 —
All 1
R
Reserved
These bits are always read as 1. The write value
should always be 1.
Note: * Only 0 can be written for flag clearing.
Rev.4.00 Mar. 27, 2008 Page 384 of 882
REJ09B0108-0400